- JEDEC standard 1.5V (1.425V ~ 1.575V) Power Supply
- VDDQ = 1.5V (1.425V ~ 1.575V)
- 800MHz fCK for 1600Mb/sec/pin
- 8 independent internal banks
- Programmable CAS latency: 11, 10, 9, 8, 7, 6
- Programmable Additive Latency: 0, CL – 2, or CL – 1 clock
- 8-bit pre-fetch
- Burst Length: 8 (interleave without any limit, sequential with starting address โ000โ only), 4 with tCCD = 4 which does not allow seamless read or write (either on the fly using A12 or MRS)
- Bi-directional Differential Data Strobe
- Internal (self) calibration: Internal self calibration through ZQ pin (RZQ: 240 ohm ยฑ 1%)
- On Die Termination using ODT pin
- Average Refresh Period 7.8us at lower than TCASE 85ยฐC, 3.9us at 85ยฐC < TCASE < 95ยฐCยบ
- Asynchronous Reset
- PCB: Height 0.740โ (18.75mm) or 1.180โ (30.00mm)
- CL(IDD): 11 cycles
- Row Cycle Time (tRCmin): 48.125ns(min.)
- Refresh to Active/Refresh Command Time (tRFCmin): 260ns(min.)
- Row Active Time (tRASmin): 35ns(min.)
- Maximum Operating Power: TBD W*
- UL Rating: 94 V – 0
- Operating Temperature: 0 โ to +85 โ
- Storage Temperature: -55 โ to +100 โ