The ADATAโs module is a 1024Mx72 bits 8GB(8192MB) DDR3-1600(CL11)-11-11-28 SDRAM memory module. The SPD is programmed to JEDEC standard latency 1600Mbps timing of 11-11-11-28 at 1.5V. The module is composed of eight-teen 512Mx8 bits CMOS DDR3 SDRAMs in FBGA package and one 2Kbit EEPROM in 8pin TDFN package on a 240pin glassโepoxy printed circuit board.
The module is a Dual In-line Memory Module and intended for mounting onto 240-pins edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges of DQS. Range of operating frequencies, programmable latencies and burst lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
Features๏ผ
โข Power supply (Normal): VDD & VDDQ = 1.5V ยฑ 0.075V
โข 1.5V (SSTL_15 compatible) I/O
โข MRS Cycle with address key programs
– CAS Latency (5,6,7,8,9,10,11)
– Burst Length (BL):8 and 4 with Burst Chop(BC)
โข Bi-directional, differential data strobe (DQS and /DQS)
โข Differential clock input (CK, /CK) operation
โข DLL aligns DQ and DQS transition with CK transition
โข Double-data-rate architecture; two data transfers per clock cycle
โข 8 independent internal bank
โข Internal (self) calibration: Internal self calibration through ZQ pin (RZQ:240 ohmยฑ1%)
โข Auto refresh and self refresh
โข Average Refresh Period 7.8us at lower then TCASE 85ยฐC, 3.9us at 85ยฐC < TCASE โค 95ยฐC
โข 8-bit pre-fetch
โข On Die Termination using ODT pin
โข Lead-free products are RoHS Compliant
Specifications:
โข Module Type: Unbuffered DIMM ECC
โข Form Factor: Standard (1.18” height)
โข Memory Type: DDR3
โข Standard: JEDEC
โข Interface: 240-pin
โข Capacity: 8GB
โข Speed: 1600MHz
โข VDD Voltage: 1.5V
โข Rank: 2
โข CAS Latency: CL11
โข Clock Rate: 800MHz
โข Timing-Cycle Time: 1.25ns
โข Refresh: Auto-refresh/Self-refresh
โข Operation Temperature: TC=0โ to 85โ
โข RoHS: Yes
โข Intel Platform: Nehalem/Westmere
โข Sandy-Bridge
โข AMD Platform: Interlagos/Valencia